1. Field of the Invention
This disclosure relates to an electronic device including a memory cell.
2. Description of the Related Art
A multilevel memory in which data with more than one bit can be stored in one memory cell and a multibit memory in which data with two or more bits can be stored in one memory cell are each a promising technology for increasing the degree of integration of a memory. The technology has already been employed in flash memories.
Patent Document 1 and Patent Document 2 each disclose a technique relating to reading of multilevel data and rewriting of the read data in a one-transistor one-capacitor DRAM cell (1T1C-DRAM).
For example, Patent Document 2 discloses a technique comprising the steps of supplying the potential of a bit line at the time when the charge of a memory cell is released (i.e., a read potential) to a plurality of sense amplifiers, electrically isolating the sense amplifiers from each other, amplifying and outputting a difference between the reference potential of each sense amplifier and the read potential in each sense amplifier, and supplying an output of only a specific sense amplifier to the bit line.